Director of Silicon Validation

We are looking for a Director of Silicon Validation to own the complete verification and validation lifecycle of our AI inference silicon, from pre-silicon functional verification, through hardware emulation, to post-silicon bring-up and production validation. This leader owns the question every tape-out depends on: is the design correct, and how do we know? The ideal candidate has led verification and validation organizations through multiple successful tape-outs, is equally at home in a System Verilog code review and in a post-silicon lab, and has built the methodology and infrastructure that lets a team scale through leverage rather than headcount alone.

This is an Austin, TX based role. We do not yet have a physical office in the area, but we are planning to open one. Once established, employees will be expected to work in a hybrid capacity, splitting time between in-office and remote work.

Verification & Validation Leadership

• Lead and grow three interlocking disciplines: pre-silicon design verification, hardware emulation, and post-silicon validation and bring-up.
• Own the verification strategy, test plans, and coverage closure criteria that gate tape-out, and make the data-driven readiness recommendation to executive leadership.

Test Strategy & Emulation Infrastructure

• Define what content runs where across simulation, emulation, FPGA prototyping, and silicon to maximize bug discovery per engineering day and per compute dollar.
• Build and scale the emulation environment into the platform that enables firmware and software bring-up well ahead of first silicon.

Post-Silicon Bring-Up & Debug

• Establish the post-silicon bring-up plan, lab infrastructure, and on-chip observability and debug strategy before tape-out, and lead the bring-up effort when silicon arrives.
• Drive bug triage, root cause analysis, escape analysis, and errata management, and own the respin-versus-workaround recommendation.

Cross-Functional Partnership & Program Infrastructure

• Partner with design, DFT, physical design, firmware, and software teams so that verification intent, debug hooks, and test content are designed in rather than bolted on.
• Own regression infrastructure, compute and license capacity planning, and continuous integration for verification and emulation workloads.
• Manage relationships with EDA and emulation vendors, verification IP suppliers, and third-party IP providers.

Team Building

• Recruit, mentor, and develop a high-performing verification and validation organization across multiple sites.

• A degree in Electrical Engineering, Computer Engineering, or a related field.
• 12+ years of experience in ASIC verification and/or silicon validation, including at least 5 years in a leadership role.
• A proven track record taking multiple complex ASICs from verification planning through successful first silicon and production ramp.
• Deep hands-on expertise in System Verilog, UVM, constrained-random verification, functional coverage, and assertion-based verification.
• Demonstrated ownership of a hardware emulation platform (Cadence Palladium, Siemens Veloce, or Synopsys ZeBu), including model build flows, capacity and partitioning, transactors, and co-emulation.
• Experience leading post-silicon bring-up, including first power-on, boot, interface training, characterization, and silicon debug.
• A strong understanding of high-speed interface and memory subsystem validation, including PCIe, LPDDR/HBM, Ser Des, and coherent interconnect.
• Working knowledge of DFT, ATPG, and MBIST, and how test structures interact with verification and bring-up.
• Experience defining verification sign-off criteria and presenting readiness data to executive stakeholders.
• Excellent leadership, communication, and cross-functional collaboration skills.

• Experience verifying and validating AI/ML accelerators, high-performance computing (HPC), or data center silicon.
• Firmware or embedded software bring-up experience, including booting a boot loader or Linux on emulation or first silicon.
• Hands-on deployment of formal verification methodology alongside simulation-based verification.
• Experience with Arm-based subsystems and coherent mesh interconnects.
• Familiarity with virtual prototyping, performance validation, and correlating silicon results to pre-silicon models.
• A track record building verification automation and applying AI-assisted tooling to verification and debug workflows.
• Experience scaling a validation organization across…