Director of Physical Design

A very well-backed startup are looking for a Director of Physical Design to guide the team through research and concept to first silicon on advanced nodes. A hands‑on technical leadership position, you will own block-level and full-chip physical design, build a team and support colleagues across digital design and verification.

Although applicants based in the Bay Area are preferred, they are willing to consider remote work with occasional travel.

• Own block-level physical design from floor planning and placement through CTS, routing and signoff.
• Drive timing, congestion, power and signal integrity optimisation.
• Execute timing closure, ECOs and physical verification, including DRC/LVS.
• Work closely with synthesis, STA, DFT and chip‑level teams to support successful integration.
• Contribute to power integrity analysis, design reviews and tapeout readiness.

• 10+ years of hands‑on ASIC/SoC physical design experience.
• Strong experience with Cadence Innovus and end‑to‑end physical design flows.
• Solid understanding of timing constraints, STA, CTS and timing closure.
• Experience with power integrity, IR drop, electromigration and physical verification.
• Strong Tcl scripting skills;
  Python or Shell experience is beneficial.
• Experience working on advanced process nodes, ideally 7nm or below.