Mid Level FPGA Engineer

• Restricted Stock and Options
• 401(k)
• Health insurance
• Paid time off
• 401(k) matching

Location: Raleigh, NC (Hybrid – Up to 2 days remote)
Job Type: Full-Time Experience Level: Mid-Level (4 to 5+ years)
Security Requirement: Ability to obtain/maintain a DoD Secret Clearance

We are seeking a skilled and motivated Mid-Level FPGA/RTL Design Engineer with a minimum of 4 to 5+ years of experience to join our engineering team in Raleigh, NC. In this role, you will own the design, implementation, and verification of digital logic targeting Xilinx and Lattice FPGA platforms, writing RTL in both Verilog and VHDL across the full development lifecycle — from architecture and simulation through synthesis, timing closure, and hardware bring-up.

This position focuses heavily on producing robust, well-verified RTL and supporting the hardware/software boundary. You will balance digital design with hands-on technical execution, including lab-based debug, hardware-software integration, and system-level troubleshooting alongside embedded software engineers.

Schedule: Hybrid environment based out of our Raleigh, NC facility, offering flexibility for up to 2 days of remote work per week. Remote work is subject to manager approval and prior authorization based on project milestones. Note that hands-on lab work, hardware debugging, and system bring-up will require an on-site presence.

Clearance: Ability to obtain and maintain a Department of Defense (DoD) Secret Security Clearance (or equivalent agency clearance).

• RTL Design & Implementation: Design and implement digital logic in Verilog and VHDL for FPGA-based systems, targeting Xilinx (e.g., Artix, Kintex, Zynq/Zynq Ultra Scale+, Versal) and Lattice (e.g., ECP5, Cross Link, Nexus/Certus Pro) device families.
• Verification: Develop test benches and perform functional simulation (Vivado Simulator, CocoTB, or similar) to validate design correctness prior to hardware bring-up.
• Synthesis & Timing Closure: Drive designs through synthesis, place-and-route, and timing closure using Vivado and Lattice Diamond/Radiant tool chains.
• Hardware/Software Integration: Collaborate closely with embedded software engineers to define and validate hardware-software interfaces (register maps, DMA, interrupts, memory-mapped peripherals) and support firmware bring-up on FPGA-hosted processors.
• Hardware Bring-up & Debug: Lead lab-based debug using ILAs, logic analyzers, oscilloscopes, and JTAG tools; troubleshoot systemic issues crossing the hardware/firmware boundary.
• Interface & Requirements Support: Interface RTL with high-speed peripherals (DDR, SPI, I2C, UART, Ethernet, PCIe, SERDES/transceivers) and support Interface Control Documents (ICDs) where FPGA I/O touches other subsystems.
• Documentation & Reviews: Participate in design reviews and produce clear documentation (design specs, verification plans, timing/constraint reports).
• Design Methodology: Contribute to improving internal RTL design methodology, IP reuse, and verification practices.

• Education: Bachelor of Science (BS) degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
• Experience: A minimum of 4 to 5+ years of professional experience writing RTL in both Verilog and VHDL, with demonstrated work on both Xilinx and Lattice FPGA platforms.
• Toolchain Proficiency: Hands-on proficiency with Vivado and Lattice Diamond/Radiant (or Lattice Propel).
• Digital Design Fundamentals: Solid understanding of clock domain crossing, timing closure, synchronous/asynchronous design, FSMs, and pipelining.
• Verification: Experience writing test benches and running simulations for functional verification.
• Embedded Software…