Remote IP Verification Engineer - SystemVerilog/UVM
Oakland, Alameda County, California, 94601, USA
Listed on 2026-11-01
-
Engineering
Test Engineer, Electronics Engineer, Validation Engineer
HCLTech is seeking a highly talented Design Verification Engineer - IP to advance innovation through IP verification and reusable verification environments. The role emphasizes System Verilog, UVM, RAL modeling, and thorough coverage closure.
The candidate will implement verification plans, directed and constrained-random tests, and collaborate with RTL and SoC teams to deliver high-quality collateral and sign-off readiness.
Join us at HCL Technologies Limited as our next Remote IP Verification Engineer
- System Verilog/UVM in CA, United States.
Consider building your career as a Remote IP Verification Engineer
- System Verilog/UVM at HCL Technologies Limited.
The Remote IP Verification Engineer
- System Verilog/UVM position in the Engineering field is open for applications.
We have an opening for a Remote IP Verification Engineer
- System Verilog/UVM in CA, United States within Engineering.
This role, Remote IP Verification Engineer
- System Verilog/UVM at HCL Technologies Limited, could be your next move.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).