Senior ASIC Verification Engineer – DFT, Tessent, Remote

Experis Technology Group is seeking a Senior ASIC Verification Engineer for a remote role in the United States. The candidate will lead DFT flows, including scan insertion and memory/logic BIST, and generate ATPG patterns for stuck-at and time‑related faults.

Collaboration across RTL, ASIC, and test teams is required to ensure robust DFT readiness. You will work with Verilog/System Verilog, Python/Tcl/C++, and Siemens Tessent tools to validate designs and drive test coverage across subsystems.

This is a strong role to take on the Senior ASIC Verification Engineer – DFT, Tessent, Remote role at Experis Technology Group.

This opening is for the Senior ASIC Verification Engineer – DFT, Tessent, Remote role at Experis Technology Group.

We are seeking a motivated Senior ASIC Verification Engineer – DFT, Tessent, Remote to join Experis Technology Group in San Jose, CA, United States.