Senior RTL Design Engineer; Fully Remote

• Design and implement RTL for complex digital subsystems.
• Perform linting, CDC analysis, and ensure synthesis readiness.
• Support integration and debug in simulation and early silicon.

• Bachelor's or Master's in EE or CE, with 5+ years of RTL design experience.
• Strong hands-on experience with Verilog/System Verilog and microarchitecture.
• Experience with simulation and debug tools (e.g., VCS, Questa, Verdi).

• Base salary range $160,000–$240,000 per year plus meaningful equity.
• Full benefits and 401(k).

• Backed by top-tier VCs and led by experienced founders.
• We value trust, integrity, and respect in our collaboration.

We are a startup building foundational technology for AI data center clusters, backed by top-tier VC firms. We are a remote-first team of experienced builders based in the U.S. and Canada, with a culture of trust, integrity, and shared responsibility.