Remote DV Engineer — SystemVerilog​/UVM Tapeout Signoff

IC Resources is seeking Design Verification Engineers for contract, W2 roles in the United States to support tapeout of high‑speed interconnect chips. You will build and extend UVM test benches, write test plans and sequences, and drive regressions to closure before fab.

Ideal candidates have 5+ years of DV experience with System Verilog/UVM, ownership of a block or subsystem through tapeout, and strong debugging skills. Familiarity with PCIe, Ethernet or DDR is a plus.

This role, Remote DV Engineer — System Verilog/UVM for Tapeout Signoff at IC Resources, could be your next career step.

We have an opening for a Remote DV Engineer — System Verilog/UVM for Tapeout Signoff in United States within IT & Technology, Engineering.

This role, Remote DV Engineer — System Verilog/UVM for Tapeout Signoff at IC Resources, could be your next opportunity.