Remote RTL Front-End Design Engineer; ASIC​/FPGA)

Turing, based in San Francisco, is seeking a front-end RTL design engineer to craft tasks for AI hardware evaluation. You will turn real RTL work into tasks and reference solutions, covering RTL, bug-fix, and PPA problems for real IP, and ensure they pass rigorous synthesis, timing, and equivalence checks.

You will work on design tasks through commercial and open-source flows, explain area, timing, and power results, and contribute to the ground-truth data used to train AI models.

This Part Time opening is for the Remote RTL Front-End Design Engineer (ASIC/FPGA) role at Humanit App.

Consider building your career as a Remote RTL Front-End Design Engineer (ASIC/FPGA) at Humanit App.

The Remote RTL Front-End Design Engineer (ASIC/FPGA) position in the IT & Technology, Engineering field is open for applications.

We have an opening for a Remote RTL Front-End Design Engineer (ASIC/FPGA) in San Francisco, CA, United States within IT & Technology, Engineering.