Principal Embedded Firmware Engineer — AI​/HPC Networking Silicon

Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation.

Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world’s most demanding computational challenges with our next-generation networking solutions.

We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles.

Cornelis Networks builds high-performance fabric solutions for AI and HPC. We're looking for a principal-level embedded engineer to help architect firmware across our next-generation networking silicon. A key focus of the role is the management firmware that boots, secures, and controls the on-chip compute engines that accelerate collective communication (all-reduce, broadcast, reduce-scatter), alongside broader embedded architecture work across the platform. You'll own the infrastructure layer that makes these engines trustworthy and production-ready, not the collective algorithms themselves.

This role is a mixture of hands-on architecture, firmware development, technical leadership, and mentorship, with heavy use of AI tools across design, implementation, and testing.

Location:

Remote (US)

• Architect and implement bare-metal C firmware on a RISC-V management core that provisions, boots, and supervises arrays of on-chip acceleration engines.
• Own the secure firmware-loading pipeline: fetch images from flash, coordinate hardware root-of-trust authentication, and distribute verified images into each engine's local memories through on-chip fan-out/DMA hardware.
• Build per-engine bring-up, reset sequencing, and health validation driven by control/status registers, with solid
  timeout and error handling and enforced security in variants.
• Scale firmware distribution and bring-up across many engines and multiple dies, including runtime re-boot and in-field firmware updates.
• Define the hardware/software contract with ASIC/RTL teams using a datamodel-first workflow (e.g., SystemRDL, Kaitai,YAML → generated code).
• Validate firmware against functional simulators (e.g., QEMU) with automated unit and integration tests.
• Set architecture standards, review designs and code, and mentor engineers.

• 10+ years of embedded/firmware engineering, with a track record of software architecture and technical leadership.
• Expert C (C++ a plus) and working Python.
• Deep experience with bare-metal firmware on constrained cores, including manually managed local memories and lowlevel bring-up.
• Experience with secure boot / image authentication and hardware root-of-trust integration.
• Experience programming hardware CSRs and co-designing register-level interfaces with silicon teams.
• Demonstrated, hands-on AI-assisted engineering proficiency, plus the judgment to validate what the AI produces.

• RISC-V firmware and toolchain experience.
• Firmware orchestration for multi-core accelerator arrays.
• Hardware root-of-trust ecosystems (e.g., Caliptra) and SHA-2/signature verification.
• Code-generation tool chains (SystemRDL, Kaitai, CMake) and simulator-based co-verification.
• Familiarity with…