Senior ASIC PD Engineer — Cache Coherent Interconnects, Equity

A leading technology company in the United States seeks a Senior ASIC Physical Design Engineer to design on-chip interconnect networks and caches. You will collaborate closely with teams to achieve timing and performance goals. Ideal candidates will have a Master's degree in Electrical Engineering and over 5 years of experience in semiconductor designs. Competitive compensation package provided, including salary range of $136,000 to $264,500.
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