Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

Senior ASIC Physical Design Engineer, Cache Coherent Interconnects at NVIDIA

Join our CPU Cache Coherent Interconnects Design Team to design the CPU on‑chip interconnect network and last‑level caches, collaborating closely with logic design for micro‑architecture definition and feasibility.

• Act as the liaison between logic and physical design teams to achieve timing, area, performance, and power goals.
• Help define the architecture for next‑generation NVIDIA coherent interconnects and system‑level caches.

• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
• 5+ years of experience in processor or high‑performance semiconductor designs.
• Hands‑on physical‑design expertise: synthesis, timing analysis, floor‑planning, and deep knowledge of industry‑standard physical‑design tools.
• Experience in high‑frequency interconnect, cache, or core design (preferred).
• Verilog expertise and deep understanding of ASIC design flow (RTL, verification, DFT, ECO) (preferred).
• Strong communication and interpersonal skills to work in a dynamic, global team.

Base salary:
Level 3 – $136,000 to $212,750, Level 4 – $168,000 to $264,500. Equity and benefits are also offered.

Applications accepted until November 23, 2025.

NVIDIA is committed to fostering a diverse work environment and is an equal‑opportunity employer. We do not discriminate based on race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.