Job Details
FPGA Design Engineer – KANATA, ON, Ottawa, Ontario, Canada
Posted: 1/13/2026
• Job
• Category:
Information Technology
• Type:
Contract
• Duration:
Long Term
• Positions: 1
Stefanini Group is hiring! We are looking for an FPGA Design Engineer with Radio experience for an on‑site role.
Contact Rahul Kumar: 248‑936‑5060 •
PTO: 10 days (80 hours accrual) + 9 holidays + 3 personal days (total 22 days)
Ideal CandidateFPGA design engineer with radio experience, 4G/5G radios, at least 7 years of experience, heavy System Verilog & RTL. VHDL is NOT used.
Tools:
Altera Quartus, MATLAB/Simulink (Axi, Ethernet prototyping).
- Work on complex problems and deliver innovative solutions.
- Use independent judgment to accomplish goals.
- Stay abreast of industry trends and communicate vision.
- Contribute research, evaluations, project plans, and budgets.
- Act as consultant on critical projects.
- Lead teams, give technical guidance and update senior management.
- Set standards and meet cost targets via design choices.
- Perform competitive analysis.
- Engage with customers and handle internal/external situations.
- Determine requirements and functional specifications under guidance.
Design & Architecture
- Develop FPGA IP architecture for 4G/5G radio units.
- Contribute to system‑level design aligned with 3
GPP and O‑RAN Alliance specs. - Implement complex RTL blocks (Verilog/System Verilog) and integrate into larger systems.
- Optimize FPGA resource utilization and ensure timing closure.
Validation & Testing
- Define and execute verification plans using UVM.
- Simulate and perform system‑level FPGA validation.
Collaboration
- Work closely with radio unit development teams.
- Partner with software teams for hardware–software interoperability.
- Mentor junior engineers and review technical work.
- Proven experience in FPGA design and RTL development.
- Expertise in /LTE/eCPRI/CPRI/PTP protocols and signal processing.
- Familiarity with JESD
204B/C, Ethernet, PCIe, AXI, high‑speed SERDES. - Tools:
Quartus, Vivado, MATLAB/Simulink, HDL Coder. - Knowledge of UVM and verification methodologies.
- Strong understanding of 4G/5G radio architecture and O‑RAN ecosystem.
- Experience with Git/Git Hub and version control workflows.
- 7+ years FPGA design experience in wireless or high‑speed systems.
- Experience with high‑volume wireless products and IP development.
- Contributions to standards bodies or technical forums (O‑RAN, 3
GPP).
Stefanini takes pride in hiring top talent. Our talent acquisition team will discuss the role and process with a phone conversation before any offer is made.
About Stefanini GroupStefanini Group is a global provider of offshore, onshore and nearshore outsourcing, IT consulting, systems integration, and staffing services. We serve Fortune 1000 enterprises across multiple industries and operate in the Americas, Europe, Africa, and Asia. The company holds CMMI Level 5 certification.
Pay: $75.00 – $78.00 per hour
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