ASIC Digital, Verification Engineer - Senior

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self‑driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high‑performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You are a highly skilled and driven ASIC Digital Verification Engineer with a passion for advancing technology and solving complex problems. With a solid foundation in digital design and verification, you thrive in fast‑paced, collaborative environments and bring a proactive mindset to every challenge. You have extensive experience in verifying complex ASIC designs, utilizing advanced methodologies such as System Verilog and UVM, and you are adept at debugging intricate testbench and design issues.

Your technical curiosity drives you to stay up‑to‑date with the latest industry trends and tools, while your organizational skills allow you to manage multiple priorities effectively. You value teamwork and open communication, and you are always eager to share your knowledge and learn from others. As a self‑learner and independent contributor, you are resourceful and take initiative in identifying and implementing innovative solutions.

Your ability to communicate complex technical concepts clearly makes you a valued collaborator within cross‑functional teams. You are motivated by the opportunity to contribute to leading‑edge projects, and you are committed to excellence in every aspect of your work. Your dedication to continuous improvement, both personally and professionally, ensures you are always pushing the boundaries of what’s possible in digital verification.

• Developing and executing comprehensive verification plans for complex ASIC designs, focusing on next‑generation HBM (High Bandwidth Memory) products.
• Writing and maintaining advanced testcases using System Verilog and UVM methodologies to ensure thorough coverage and robust verification.
• Debugging and analyzing complex testbench and design‑related issues, collaborating closely with design and mixed‑signal engineering teams.
• Automating verification flows and processes using scripting languages such as Python or Perl to enhance productivity and coverage.
• Reviewing and providing feedback on design specifications, contributing to architecture and design discussions to improve product quality.
• Participating in code reviews, mentoring junior engineers, and sharing best practices within the verification team.
• Documenting verification results, methodologies, and lessons learned to support knowledge sharing and process improvement.

• Accelerating the development of high‑performance, reliable HBM solutions that power the next generation of computing and AI applications.
• Ensuring the delivery of robust, high‑quality silicon products through meticulous verification and debugging.
• Driving innovation in verification methodologies and contributing to the continuous improvement of engineering processes.
• Reducing time‑to‑market for cutting‑edge products by identifying and resolving issues early in the design cycle.
• Enhancing team capabilities by sharing knowledge, mentoring peers, and fostering a collaborative engineering environment.
• Influencing the direction of future product development by providing valuable insights into design and verification challenges.

• Bachelor’s or Master’s degree in Electrical Engineering (BSEE or MSEE) with a minimum of 10 years of digital design/verification experience.
• Proven experience in writing and maintaining testcases using System Verilog/UVM.
• Strong debugging skills for complex testbench and design‑related issues.
• Solid understanding of digital circuit design concepts and principles.
• Proficiency with scripting languages such as Python or Perl for automation and workflow enhancement.
• Demonstrated ability to work independently and as part of a team in a dynamic engineering environment.