Digital Design Engineer – Digital Synchronization

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Digital Design Engineer – Digital Synchronization page is loaded## Digital Design Engineer – Digital Synchronizationlocations:
Ottawa time type:
Full time posted on:
Publié aujourd'huijob requisition :
R028718

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions, and are one of the main contributors to Ciena's success in the telecommunications industry. To further strengthen our team, we are looking for an enthusiastic digital design engineer who will be involved in the design of these products, working within a team of digital design engineers, verification engineers and architects.

Your role as a digital design engineer will focus on digital synchronization and digital PLL development, in which you will propose innovative solutions, in order to design power and area optimized timing and synchronization related functional blocks and algorithms for the Wavelogic family of products.
* You are expected to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects
* You will focus on the digital PLL development, jitter, wander and synchronization functions and will define algorithms to extract and propagate source timing and rate information form standard client protocols across the digital optical network.
* You will produce an implementation specification document and have it reviewed by your team, architects and analog/board designers if applicable
* You are accountable for the creation and integration of new and existing RTL and/or C source code, algorithms and functions
* You are responsible for designer testing of your code as well as debugging of your code during simulation, regression and formal verification
* You will assist the verification team in determining coverage and provide design assertions and waivers as needed
* You are held responsible for crafting timing constraints for your code, and will participate in synthesis log reviews, constraint reviews, timing report analysis, layout and backend reviews
* You will be involved in lab validation of the product and its prototype
* You are expected to report on status updates on a regular basis
* Electrical or computer engineering or other applicable scientific degree at the BEng/BSc or MEng/MSc level
* Knowledge and experience with system timing and synchronization algorithms, digital PLL design for timing extraction, rate matching, protocol mapping (e.g. GMP, BMP)
* Knowledge and experience with digital filter design, Matlab modeling
* A highly motivated self-starter, able to work independently, while being a great teammate
* Ability to methodically solve complex technical problems
* Excellent organization, written and oral (English) communication skills
* Proficiency above the intermediate level with use of System Verilog for design
* Familiarity with digital (including formal) verification methods
* Experience with digital design synthesis, STA, timing closure and asynchronous clock crossing
* Good understanding of timing/power/area analysis and trade-offs
* Experience with digital ASIC design backend process
* Experience with digital design for low power
* Experience with standards and…