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Job Description & How to Apply Below
A global technology company in Ottawa is on the lookout for a passionate ASIC Digital Design engineer. This role demands 7-10 years of experience in RTL design focusing on high-speed digital interfaces. The ideal candidate will be responsible for developing innovations in HBM PHY IP, working closely with diverse teams to solve complex engineering challenges. Strong expertise in System Verilog and Verilog, alongside excellent problem-solving skills, is essential for success in this dynamic and fast-paced environment.
Join us to drive the future of semiconductor technology.
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Position Requirements
10+ Years
work experience
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