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Senior ASIC RTL Architect — HBM IP Speed Design

Job in Ottawa, Ontario, Canada
Listing for: Synopsys Inc
Full Time position
Listed on 2026-02-28
Job specializations:
  • Engineering
    Systems Engineer
Salary/Wage Range or Industry Benchmark: 150000 - 200000 CAD Yearly CAD 150000.00 200000.00 YEAR
Job Description & How to Apply Below
Position: Senior ASIC RTL Architect — HBM IP & High‑Speed Design
A global technology company in Ottawa is on the lookout for a passionate ASIC Digital Design engineer. This role demands 7-10 years of experience in RTL design focusing on high-speed digital interfaces. The ideal candidate will be responsible for developing innovations in HBM PHY IP, working closely with diverse teams to solve complex engineering challenges. Strong expertise in System Verilog and Verilog, alongside excellent problem-solving skills, is essential for success in this dynamic and fast-paced environment.

Join us to drive the future of semiconductor technology.
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Position Requirements
10+ Years work experience
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