Senior ASIC Design Engineer at Ciena

Elevate your career as a Senior Digital ASIC Design Engineer with Ciena in Ottawa. This full-time role focuses on ASIC design and integration for innovative Wave Logic products.

Ciena seeks an experienced engineer with over five years in ASIC design to contribute to high-performance optical networking solutions. You will collaborate across teams, interpret architecture, and develop top-level RTL designs, alongside maintaining technology-specific libraries. This role ensures the delivery of quality silicon for telecommunications infrastructure.

Key Responsibilities:

• Contribute to ASIC design and integration for Wave Logic technology

• Develop and assemble top-level RTL integrating multiple IP blocks

• Analyze synthesis, timing, layout, and backend reports

• Create timing constraints to support designs

• Validate ASIC prototypes and production silicon in lab settings

Requirements:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science

• 5+ years of ASIC design experience

• Proficiency in Verilog, System Verilog, and Python

• Strong analytical and problem-solving skills

• Excellent communication within technical environments

Make an impact at Ciena by leading the next generation of ASIC technologies.
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