Senior Verification Engineer

Job Details

Intel is seeking a highly qualified candidate to join our ASIC design verification team in a dynamic and forward‑thinking organization focused on next‑generation semiconductor product development. Our team focuses on being nimble, adaptable, lean and efficient to drive cutting‑edge, customer‑impacting technology development. We embrace innovative and efficient methodologies that drive at‑scale product execution.

Advance your career with cutting‑edge verification techniques including coverage‑driven verification, formal methods, and performance analysis. Lead custom System Verilog/UVM development, master industry‑standard EDA tools, architect verification strategies for complex ASICs, and mentor emerging talent while independently driving verification closure. Join our fast‑paced semiconductor team where your technical leadership shapes next‑generation chip development through comprehensive methodologies and innovative verification solutions. Transform challenging projects into career‑defining achievements.

If you are passionate about building products faster and more efficiently than anyone else on the planet, we want you on our team.

• Define Project Specific Verification Strategy: defines and implements scalable and reusable verification plans, test benches, and the verification environments for blocks, subsystems, and SoCs. Ensure meeting the required coverage levels and conform to microarchitecture specifications.
• Lead Verification Execution: create detailed test plans and drive technical reviews with design and architecture teams to validate these plans and proofs.
• Execute verification plan: implement and run block/subsystem/cluster/SoC simulation models to verify the design, analyze power and performance, and identify bugs.
• Investigate and Resolve Bugs: replicate, root‑cause, and debug issues in the pre‑silicon environment. Find and implement corrective measures to resolve failing tests.
• Collaborate Across Teams: work closely with SoC architects, micro‑architects, full chip architects, RTL developers, post‑silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
• Enhance Future Verification Methodologies: continuously improve existing functional verification infrastructure and methodologies.
• Absorb learnings: from post‑silicon on the quality of validation done during pre‑silicon development, update test plan for missing coverages and proliferate to future products.
• Lead and mentor others: inspire and guide junior engineers, fostering their growth and development. Your expertise will be instrumental in cultivating a collaborative and innovative environment where every team member thrives.

• Bachelor's degree in electrical engineering, computer engineering, computer science, or other relevant STEM related degree.
• 5+ years of experience in ASIC/FPGA design verification.
• Experience in developing UVM and/or Formal based verification architectures and methodologies.
• Experience with industry‑standard protocols such as AMBA AXI/AXI‑S/CHI/APB and low‑speed communication protocols such as UART, SPI or I2C/I3C.
• Hands‑on experience with simulators (Synopsys VCS, Cadence Xcelium, or equivalent).
• Experience with coverage‑driven verification, constrained‑random testing and strong debugging skills.
• Experience with scripting languages such as Python, TCL, and Shell scripting.

• Graduate/post‑graduate degree in electrical engineering, computer engineering, computer science, or any STEM related degree with overall 8+ years of experience.
• Skilled in various validation concepts and debug techniques relevant to ASIC/FPGA domain.
• Collaborative, able to communicate well with counterparts and stakeholders.
• Strong written and verbal communication skills.
• Strong analytical ability and problem‑solving skills.
• Experience in defining testbench architecture, constrained random verification methodologies.
• Experience in processor‑based verification using C/C++ with UVM‑based verification environments.
• Define and execute validation of IPs and/or SoC from spec to tape‑in including setting…