Senior Memory Layout Engineer

Position: Senior Memory Layout Engineer TSMC
Advance your technical skills as a Senior Memory Layout Engineer at TSMC Technology in Ottawa, Canada. Focus on custom layout designs and participate in cutting-edge R&D projects under advanced processes.

In this senior role, you will implement custom layouts for high-density, high-speed memory compilers and analog circuits utilizing deep-submicron CMOS/FinFET technologies. You will coordinate layout projects while leveraging your 8+ years of advanced semiconductor memory layout design experience. Proficiency in FinFET nodes, layout verification tools, and scripting is essential for success.

Key Responsibilities:

• Design custom layouts for memory arrays and periphery

• Utilize CAD tools for layout, DRC, LVS, and RC extraction

• Estimate, plan, and coordinate layout work effectively

• Demonstrate expert knowledge of advanced layout techniques

• Write scripts using Cadence Skill, TCL, and Linux

Requirements:

• Bachelor's or master's in Computer Science, Engineering, or related field

• Over 8 years of experience in memory layout design

• Familiarity with verification tools like ICV and Calibre

• Knowledge of ESD and latch-up layout techniques

• Strong understanding of memory circuit documentation

Become a key player at TSMC by showcasing your expertise in memory layout design and project leadership.
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