FPGA Developers; Radio Expertise - 4G​/5G - DataPath Side of RU Design

Must Understand Data Path Side of RU FPGA Design Responsibilities

• Works on unusually complex problems and provides highly innovative solutions.
• Uses independent judgment to accomplish goals and objectives.
• Has insight into industry trends and communicates vision to guide organizational strategy and long‑range planning.
• Lends research and contributes to evaluations, project plans and budgets for new products or updates existing products.
• Acts as consultant on critical projects that impact long‑term organizational goals and objectives.
• Leads teams, gives technical guidance and communicates with senior management on progress; identifies or creates solutions that are likely to contribute to the development of new company concepts.
• Expected to set standards and achieve cost targets for product cost through proper design choices, component selection or supplier selection.
• Demonstrated expertise in competitive analysis.
• May actively seek customer input and take responsibility for internal and external customer situations.
• Determines requirements and functional specifications for entire system, under only consultative direction.

• Develop FPGA IP architecture for 4G/5G Radio Units.
• Contribute to system‑level design aligned with 3
  
  GPP and O‑RAN Alliance specifications.

• Implement complex RTL blocks (Verilog/System Verilog/VHDL) and integrate into larger systems.
• Optimize FPGA resource utilization and ensure timing closure.

• Define and execute verification plans using UVM and advanced techniques.
• Perform simulation and system‑level FPGA validation.

• Work closely with Radio Unit development teams for seamless integration.
• Partner with software teams to ensure hardware‑software interoperability.
• Mentor junior engineers and participate in technical reviews.

• Proven experience in FPGA design and RTL development.
• Expertise in /LTE/eCPRI/CPRI/PTP protocols and signal processing.
• Familiarity with JESD
  204B/C, Ethernet, PCIe, AXI, and high‑speed SERDES.
• Tools:
  Quartus, Vivado, MATLAB/Simulink, HDL Coder.
• Knowledge of UVM and verification methodologies.
• Strong understanding of 4G/5G Radio architecture and O‑RAN ecosystem.
• Experience with Git/Git Hub and version control workflows.

• 7+ years of FPGA design experience in wireless or high‑speed systems.
• Experience in high‑volume wireless products and IP development.
• Contributions to standards bodies or technical forums (O‑RAN, 3
  
  GPP).