Senior ASIC Engineer

Position: Senior ASIC Engineer at Ciena
Shape the future of optical networking as a Senior ASIC Engineer us on synthesis, static timing analysis, and critical frontend implementation tasks to drive innovative solutions.
Ciena is seeking a Senior ASIC Engineer to contribute to the Wavelogic DSP programs. This pivotal role emphasizes synthesis and logical equivalence checking, ensuring functional integrity through clock domain validation. Collaboration with diverse engineering teams is crucial for seamless integration and comprehensive design validation, making a significant impact in high-speed optical technologies.

Key Responsibilities:

• Perform synthesis for ASIC designs and validate clock domains

• Create and optimize scripts to enhance workflows

• Maintain essential timing constraints for effective integration

• Validate designs during both pre and post-layout stages

• Collaborate with IP development and EDA partners
Requirements:

• Degree in Electrical or Computer Engineering

• Extensive experience in static timing analysis for ASICs

• Familiarity with ASIC implementation and RTL design

• Experience managing project deliverables

• Proficiency in automation scripting for design workflows
Utilize your synthesis and engineering skills to drive innovation in optical networking at Ciena.
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