Senior R&D Engineer at Synopsys

Drive innovation in silicon design with Synopsys as a Senior R&D Engineer. Leverage your expertise in Python automation and analog design flow to enhance engineering efficiency.
At Synopsys, you will utilize your 6+ years of experience in VLSI design and EDA tool development to support global foundation IP R&D teams. Collaborate closely with design teams to streamline analog design flows, tackle complex issues, and implement automation that enhances productivity. Your ability to identify root causes and foster smooth integration of EDA tools will be essential to the team's success.

Key Responsibilities:

• Develop and debug analog design flows for global projects

• Debug design issues across physical verification and extraction

• Build automation using Python, TCL, and shell scripting

• Configure IP project environments with Perforce and LSF

• Collaborate with design teams to eliminate bottlenecks
Requirements:

• MSEE or BSEE with VLSI emphasis

• 6+ years in VLSI design or design flow engineering

• Strong knowledge of analog circuit design

• Proficiency in Python and scripting

• Solid Linux/Unix command-line skills
Enhance your engineering skills and contribute to advanced solutions at Synopsys while shaping the future of silicon design.
#J-18808-Ljbffr