Memory Layout Engineer Advanced Nodes

Position: Memory Layout Engineer for Advanced Nodes
Elevate high-performance semiconductor designs as a Memory Layout Engineer. Utilize advanced node technologies to create and optimize custom memory layouts in TSMC FinFET processes.
We are seeking a skilled engineer to support memory layout development in advanced technology nodes. Your expertise should include hands-on experience in physical verification and top-level memory integration for SRAM and various memory architectures. Collaboration with circuit design and physical design teams is essential to ensure optimal performance and quality throughout the design process.

Key Responsibilities:

• Design and implement custom layouts for memory blocks

• Develop and optimize layouts for critical memory components

• Perform top-level memory integration within the SoC environment

• Execute physical verification checks and density checks

• Drive layout cleanup and signoff for tapeout readiness
Requirements:

• Bachelor’s/Master’s in Electrical/Electronics Engineering

• Proven memory layout design experience at advanced nodes

• Hands-on experience with TSMC 7nm FinFET technology

• Familiarity with layout and verification tools like Virtuoso

• Strong understanding of memory architecture and methodology
Bring your memory layout expertise to support cutting-edge semiconductor technology.
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