Layout Engineer

We are looking for a highly skilled Memory Layout Engineer with strong expertise in advanced node technologies to support high‑performance semiconductor designs. The ideal candidate will have hands‑on experience in memory layout development, physical verification, and top‑level integration across SRAM and other memory architectures on TSMC FinFET processes .

• Design and implement custom layouts for memory blocks , including
• Develop and optimize layouts for critical memory components such as
• Perform top‑level memory integration , ensuring seamless assembly of memory macros within SoC environment
• Execute and resolve physical verification checks , including Density check
• Drive layout cleanup and signoff closure , ensuring high‑quality tapeout readiness
• Analyze and mitigate IR drop and EM (Electromigration) issues in memory layout
• Collaborate with circuit design, physical design, and process teams to ensure optimal performance, area, and power

• Bachelor’s/Master’s degree in Electrical/Electronics Engineering or related field
• Proven experience in memory layout design at advanced technology node
• Hands‑on experience with TSMC 7nm FinFET technology

• Experience with TSMC 6nm / 5nm / 4nm / 3nm technology
• Strong understanding of memory architecture and layout methodology
• Familiarity with industry‑standard layout and verification tools (e.g., Virtuoso, Calibre)

• Physical verification (DRC, LVS, Density)
• IR/EM analysis and mitigation
• Top‑level memory integration
• Strong problem‑solving and debugging skill