Senior ASIC Verification Engineer at Synopsys

Drive innovation as a Senior ASIC Verification Engineer erage your System Verilog and UVM expertise to deliver high-performance memory interface IP in a collaborative environment.
In this pivotal senior staff role, you will develop comprehensive verification test plans and create robust test cases using UVM and System Verilog. With your meticulous debugging skills and analytical mindset, you will solve intricate verification challenges and ensure product reliability. You'll actively mentor junior engineers, fostering growth and innovation while collaborating closely with architecture teams to drive consensus.

Key Responsibilities:

• Develop verification test plans ensuring robust memory interface IP verification

• Create UVM testbench and test cases for RTL PHY firmware

• Collaborate through technical reviews with architecture and implementation teams

• Debug and solve verification challenges using advanced tools

• Mentor and guide junior engineers for skill development
Requirements:

• Expertise in System Verilog and simulation tools

• Proficient in scripting languages like Python or Perl

• Experience in Linux development environments

• Strong knowledge of UVM and memory interface protocols

• Bachelor’s degree in Engineering or related field
Bring your passion for technology and innovation to accelerate the development of next-generation memory interface IP.
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