Ciena ASIC Engineering Co-op

Position: Ciena ASIC Engineering Co-op Opportunity
Explore your passion for engineering as an ASIC Engineering Co-op with Ciena, an innovator in high-speed connectivity. Collaborate in a flexible work environment perfect for career growth.
During this four-month term from September to December 2026, you will join the DSP ASIC development team r contributions will include assisting with design and verification processes for leading-edge ASICs, working on module coding, and testing functionalities. Engage with tools and coding scripts that enhance team output while growing your technical skills in a supportive setting.

Key Responsibilities:

• Assist with optimizing module coding activities

• Conduct verification tests on design blocks

• Develop environments to support functional testing

• Create coding scripts to improve productivity

• Work closely with engineers on design tasks
Requirements:

• Pursuing a Bachelor's degree in relevant engineering field

• Foundational knowledge of digital logic and circuit design

• Proficiency in programming languages like C++ or Python

• Familiarity with design using Verilog or VHDL is advantageous

• Experience with DSP preferred
Transform your engineering insights into real-world impact at Ciena, emphasizing innovation and inclusivity.
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