ASIC Design Engineer

Celero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to the development of optical transceivers for next-generation optical modems. The ideal candidate will play a crucial role in designing and developing ASICs for cutting‑edge technologies.

• Design and implement digital circuits using HDL (Verilog/ System Verilog).
• Perform synthesis, timing analysis, Lint, formal equivalence, Clock Domain Crossing (CDC) analysis.
• Optimize designs for performance, power, and area (PPA) requirements.
• Perform RTL simulation and verification to ensure design functionality.
• Participate in design reviews and provide technical guidance to team members.
• Collaborate with cross‑functional teams on system integration and validation.

• Bachelor’s or higher degree in Electrical Engineering, Computer Engineering, or a related field.
• 4+ years of experience in digital design and verification.
• Proficiency in HDLs such as Verilog, or System Verilog.
• Strong understanding of digital design principles and methodologies.
• Familiarity with ASIC design flow, and experience with ASIC design tools.
• Knowledge of low‑power design techniques.
• Familiarity with verification methodologies (e.g., UVM, formal verification).
• Excellent problem‑solving, strong communication and teamwork skills.

• Strong knowledge of Digital Signal Processing (DSP), Digital Communication, and Forward Error Correction (FEC) techniques.
• Experience with scripting languages (e.g., Python, Tcl).
• Understanding of Optical Communication Standards is a plus.
• Ability to multitask and adapt to a fast‑paced, dynamic environment.

As set forth in Celero Communications, Inc.’s Equal Employment Opportunity policy,we do not discriminate on the basis of any protected group status under any applicable law.