Lead ASIC Physical Design Engineer

Position: Lead ASIC Physical Design Engineer Role
Elevate semiconductor technology at Synopsys as a Lead ASIC Physical Design Engineer. Your skills in complex SoC designs will directly contribute to groundbreaking silicon solutions.

As part of Synopsys, you will utilize your 6 to 7 years of ASIC physical design experience to lead the implementation of test chips across multiple protocols. Your thorough understanding of the physical design flow will be crucial in achieving timing closure and oversight of design verification processes. Collaborating with diverse teams, you will enhance product reliability and accelerate time-to-market.

Key Responsibilities:

• Own physical design for test chip architectures

• HQ static timing analysis and physical verification management

• Lead the RTL-to-GDSII optimization efforts

• Automate tool flows to enhance design productivity

• Collaborate across teams for efficient test chip development

Requirements:

• 6 to 7 years of experience in ASIC physical design

• Comprehensive knowledge of the complete design flow

• Familiarity with state-of-the-art CAD tools like IC Compiler II

• Proven ability to coordinate complex projects

• Strong analytical and communication capabilities

Shape the future of technology at Synopsys by applying your expertise in ASIC design.
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