Principal ASIC Design Engineer

About the role

As a Principal ASIC Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will collaborate with PD, DFT, STA, and integration teams to ensure successful tape‑outs and work closely with system teams for chip bring‑up and validation.

• BS/MS degree in Electrical Engineering or Computer Science.
• 10+ years of relevant ASIC design experience.
• Strong understanding of digital logic design and complex synchronous/asynchronous interfaces.
• Proficiency in Verilog/System Verilog RTL design.
• Experience in high-speed Serdes design and familiar with Ethernet (802.3) standards.
• Knowledge of synthesis and static timing analysis.
• Experience developing test benches and test cases; familiarity with UVM.
• Experience with gate-level simulations, chip bring‑up, and validation.
• Proven track record of successful production tape‑outs.

• Expertise in scripting languages (Python, Tcl, Perl, Shell).
• Familiarity with DFT methodology and physical design flow.
• Knowledge of UCIE, or UAlink, AXI/CHI interface is a plus.
• Hands‑on experience with STA and timing closure.
• Strong problem‑solving and planning skills.
• Excellent communication and collaboration abilities.

• Design, implement, and debug complex logic blocks.
• Integrate complex IPs from internal and external vendors.
• Support front-end integration activities such as Lint, CDC, synthesis, and ECO.
• Participate in design and code reviews to ensure quality.
• Develop functional tests/test benches and run RTL and gate-level simulations.
• Work with verification, DFT, and physical design engineers to achieve successful tape‑outs.
• Bring up, validate, and debug chip features; collaborate with software, firmware, and systems teams.

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