Memory Layout Engineer TSMC Expertise

Position: Memory Layout Engineer with TSMC Expertise
Drive innovative semiconductor designs as a Memory Layout Engineer specializing in TSMC FinFET technology. Utilize your skills to develop critical memory layouts for advanced nodes.

We are on the lookout for a Memory Layout Engineer with demonstrated experience in memory layout design at advanced nodes. This role focuses on physical verification, layout cleanup, and top-level integration for SRAM and other architectures. Collaboration with multi-disciplinary teams is essential for optimizing performance and ensuring quality assurance.

Key Responsibilities:

• Create and implement custom layouts for memory blocks

• Optimize critical memory component layouts

• Carry out top-level memory integration tasks

• Conduct physical verification checks effectively

• Lead layout cleanup initiatives for high-quality tapeouts

Requirements:

• Bachelor’s/Master’s degree in Electrical/Electronics Engineering

• Proven track record in memory layout design

• Experience with TSMC 7nm FinFET technology

• Familiarity with industry-standard tools like Calibre

• Excellent skills in IR drop and EM analysis

Bring your advanced memory layout expertise to enhance semiconductor innovation.
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