UVM Verification Engineer Position

Position: Synopsys UVM Verification Engineer Position
Enhance your career at Synopsys as a UVM Verification Engineer, specializing in memory interface IP development in a collaborative environment.

Your role will focus on innovative silicon solutions and complex design challenges.

You will lead the development of verification test plans and UVM testbench frameworks, collaborating closely with various engineering teams. Mentoring junior engineers will also be an integral part of your contributions as you work to ensure the highest quality in next-generation technologies.

Key Responsibilities:

• Develop comprehensive verification test plans for memory interface IP

• Design and implement UVM testbench infrastructure

• Collaborate through technical reviews with engineering teams

• Diagnose complex verification challenges using advanced tools

• Mentor junior engineers in best practices and technical skills

Requirements:

• Proficient in System Verilog and UVM

• Bachelor's degree in Electrical or Computer Engineering

• Experience with scripting languages like Python

• Familiar with Linux development environments

• Knowledge of memory interface standards is a plus

Contribute your innovative mindset and verification expertise to propel Synopsys’s semiconductor technology forward.
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