Synopsys ASIC Design Verification Expert

Join Synopsys as an ASIC Design Verification Expert, specializing in High-Bandwidth Memory (HBM) technologies.

Your role will leverage cutting-edge verification skills in System Verilog/UVM to solve complex challenges.

As a Staff Digital Verification Engineer at Synopsys, you will be pivotal in improving ASIC design verification processes. This position empowers you to verify RTL designs, track verification plans, and employ System Verilog/UVM test benches. Collaborate with a dynamic team of digital verification specialists to ensure high-quality designs and fast time to market for innovative products in a collaborative environment.

Key Responsibilities:

• Conduct verification of ASIC RTL designs at multiple levels

• Develop and maintain robust verification test plans

• Utilize System Verilog/UVM for test bench creation

• Evaluate functional coverage and write assertions

• Identify and resolve debugging issues within RTL simulations

Requirements:

• BSEE or MSEE plus 2+ years in digital design/verification

• Proven skill in writing System Verilog/UVM test cases

• Solid debugging experience for test benches and designs

• Proficient in Python or Perl for scripting

• Strong communication and organizational skills

Drive your career advancement by contributing to high-quality silicon IP solutions at Synopsys.
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