Senior Memory Layout Engineer Position

Join a leading semiconductor firm in Ottawa, Ontario as a Senior Memory Layout Engineer, specializing in advanced node technologies such as TSMC FinFET. Bring your memory layout design expertise to the forefront.

We are looking for a highly skilled Memory Layout Engineer with extensive experience in memory design and integration. This role focuses on advanced technologies, supporting high-performance semiconductor designs while ensuring quality and performance are prioritized. Your responsibilities will include physical verification and collaborating with design teams to maintain excellence.

Key Responsibilities:

• Design layouts for various memory structures: SRAM, ROM, TCAM

• Optimize critical components such as control circuits and decoders

• Conduct top-level integration of memory macros in SoC environments

• Carry out physical verification processes: DRC, LVS, and density

• Resolve IR-drop and electromigration issues in memory layouts

Requirements:

• Bachelor’s/Master’s degree in Electrical/Electronics Engineering

• Proven experience in memory layout design at TSMC advanced nodes

• Hands-on experience with 7nm FinFET technology

• Strong background in memory architecture and layout methodologies

• Knowledge of standard verification tools like Calibre and Virtuoso

Your excellence in memory layout design will propel innovative semiconductor technology and development efforts forward.
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