Speed Analog Layout Engineer

Position: High-Speed Analog Layout Engineer Role
Join Celero Communication Inc. as a High-Speed Analog Layout Engineer, leading complex analog designs for AI and data center applications from our locations in Irvine, CA, San Jose, CA, or Ottawa, Canada. This position focuses on layout excellence and cross-functional collaboration.

At Celero, you will utilize your extensive background in analog/mixed-signal design as a key member of our semiconductor start-up. Your leadership will help foster best practices while engaging with international teams on critical projects involving high-performance analog circuits. You’ll ensure stringent verification processes while mentoring colleagues for enhanced team effectiveness.

Key Responsibilities:

• Oversee physical layout design from planning to verification

• Collaborate on performance-optimized layout solutions

• Guide junior engineers and enforce layout best practices

• Conduct LVS, DRC, PERC, and ERC checks using standard tools

• Support integration and routing of chip-level components

Requirements:

• 10+ years in layout design specifically for analog/mixed-signal

• Experience with advanced CMOS and FinFET technology nodes

• Leadership in managing complex macro layouts

• Strong knowledge of layout verification and signoff flows

• Excellent organizational and communication skills

Bring your passion for layout design to help shape innovative AI solutions at Celero.
#J-18808-Ljbffr