Senior ASIC Digital Design Engineer at Synopsys

Drive innovation at Synopsys as a Senior ASIC Digital Design Engineer. Your expertise in RTL design and high-speed digital interfaces will shape the future of memory technologies.

With 7-10 years of hands-on experience, you’ll develop high-performance RTL designs for High Bandwidth Memory PHY IP. Collaborate with cross-functional teams, and tackle complex technical challenges while ensuring seamless integration and performance optimization. Your communication skills will be vital in mentoring junior engineers and guiding technical efforts within the team.

Key Responsibilities:

• Develop RTL designs for High Bandwidth Memory PHY IP

• Translate architectural requirements into robust RTL implementations

• Collaborate with teams for optimal integration and performance

• Innovate solutions for timing closure and low-power design

• Automate design tasks using scripting languages

Requirements:

• 7-10 years of experience in RTL design

• Proficient in System Verilog and Verilog

• Strong background in high-speed design techniques

• Experience with ASIC development flow and debugging

• Ability to write detailed specification documents

Become a key player in Synopsys’ memory interface IP leadership by leveraging your design expertise.
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