Analog Design, Sr Staff Engineer

Descriptions & Requirements

Job Description and Requirements

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You have spent years designing analog and mixed signal circuits where a few millivolts matter and where the difference between a PHY that ships and one that does not is often a layout decision you made three months ago. You know CMOS fundamentals from debugging real silicon, not from textbooks. You have seen your VCO phase noise spike after tape-out and figured out why your driver eye diagram collapsed when you moved to FinFET.

You think in trade-offs. Power, area, and speed are not abstract metrics for you. They are real decisions you make with a layout engineer and an open simulator, choices that determine whether this IP wins at a Tier 1 customer. Leadership for you is not about title. It is about being the person the team turns to when a DLL is not locking or when a customer asks why your jitter spec looks different.

You can explain a complex circuit trade-off in two sentences without losing the nuance, and you push back when a requirement does not make electrical sense. At Synopsys, you will work on memory PHY IP that powers the products the world designs.

• Provide technical leadership and direction for a local schematic design team working on DDR, LPDDR, HBM, and Mobile Storage PHY circuits
• Design and optimize high-speed analog and mixed signal circuits including receive equalizers, samplers, voltage and current-mode drivers, serialize rs, deserializers, VCOs, phase mixers, DLLs, PLLs, bandgap references, ADCs, and DACs
• Identify and refine circuit architectures to meet aggressive power, area, and performance targets across advanced FinFET process nodes
• Develop simulation and verification strategies using SPICE simulators, Verilog-A behavioral models, and custom scripting to ensure design quality and corner coverage
• Collaborate with layout engineers to minimize parasitic effects, manage device stress, and account for process variation in physical implementation
• Present simulation data, design reviews, and trade-off analyses to internal teams and external customers
• Document design specifications, test plans, and circuit features for IP product releases and customer engagements

• Your circuits will be integrated into memory PHY IP used by leading semiconductor companies to enable next-generation AI, mobile, and compute products
• Your technical leadership will shape the design quality and delivery timelines for a high-performing analog design team in Ottawa
• Your design strategies will directly influence whether Synopsys wins competitive sockets at Tier 1 customers based on power, performance, and area metrics
• Your collaboration with digital designers and layout engineers will reduce design iterations and improve time to market for critical IP releases
• Your simulation methodologies and verification rigor will catch issues before tape-out, reducing costly respins and accelerating customer adoption
• Your documentation and design reviews will set the standard for how the team communicates complex trade-offs internally and to customers
• Your expertise in FinFET design and high-speed circuits will help the team navigate process technology transitions and maintain competitive advantage

• PhD with 5+ years or Master's with 8+ years of hands‑on analog IC design experience
• Deep expertise in transistor-level circuit design with strong CMOS fundamentals, proven through multiple tape‑outs
• Detailed design experience with at least one and familiarity with several DDR or Ser Des sub‑circuits such as receive equalizers, samplers, drivers, serialize rs, deserializers, VCOs, phase mixers, DLLs, PLLs, bandgap references, ADCs, or DACs
• Proficiency with SPICE simulators and simulation…