R&d Engineer Analog Design Flows

Join Synopsys as an R&D;
Engineer specializing in analog design flows. Use your expertise in EDA tools and Python to accelerate innovation in silicon development. In this role, you will bring over 6 years of hands‑on VLSI design experience to support the silicon design team at Synopsys.

Your responsibilities will include maintaining and improving analog design flows, debugging complex physical verification issues, and automating manual processes with scripting. Collaborating with design teams, you will address limitations in design environments and streamline workflows.

• Maintain and develop analog design environments for projects.
• Debug VLSI design issues across EDA tools.
• Automate processes using Python and shell scripts.
• Configure project environments with Perforce and LSF scheduling.
• Work with design teams to find and fix bottlenecks.

• BSEE or MSEE degree focusing on VLSI.
• 6+ years in EDA tool or design flow engineering.
• Deep understanding of analog circuit fundamentals.
• Solid Python and scripting skills.
• Proficient in Linux/Unix environments.

Drive efficiency in silicon design while enhancing your technical prowess at Synopsys.