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Job Description & How to Apply Below
In this position, you will utilize your experience in deep submicron CMOS and BiCMOS technologies. With over 5 years in the field, you’ll collaborate with senior designers to optimize analog layouts for high-speed circuits, particularly DAC and ADC solutions. Your expertise will be vital for mentoring junior team members and enhancing the team's overall productivity.
Key Responsibilities:
• Develop block and macro level layouts with precision
• Conduct feasibility studies for circuit designs
• Write automation scripts for layout enhancements
• Perform thorough verification checks for layout quality
• Mentor junior layout engineers for knowledge sharing
Requirements:
• Bachelor’s in Electrical Engineering or related field
• 5+ years in custom analog layout design
• Proficiency in Cadence Virtuoso and similar tools
• Strong analytical and problem-solving skills
• Familiarity with semiconductor manufacturing processes
Shape the future of networking technology with Ciena by leveraging your analog layout expertise.
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