Digital Verification Engineer

Position: Digital Verification Engineer at TSMC
Elevate digital circuit design with TSMC Design Technology Canada Inc. as a Digital Verification Engineer in Kanata, Ontario. Focus on validating implementations, developing test benches, and troubleshooting tests every day.

As a Digital Verification Engineer, your role includes working closely with design teams to ensure the rigor of digital circuits. Leverage your industry experience between 5-10 years and expertise in System Verilog and UVM to customize verification methodologies. You'll also contribute to enhancing the electronic design automation tools and practices within the group to drive efficiency.

Key Responsibilities:

• Validate digital circuit implementations in collaboration with design teams

• Develop robust simulation test benches for verification

• Perform functional verification and debug failing tests

• Prepare manufacturing/tester patterns as needed

• Enhance EDA capabilities and methodologies in the team

Requirements:

• Master's or PhD in electrical/computer engineering

• 5-10 years in digital verification industry

• Proficient in System Verilog and UVM methodologies

• Skilled in debugging tools and Unix/Linux

• Excellent problem-solving and communication skills

Focus on digital design validation and improve EDA tools while thriving at TSMC in Kanata.
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