ASIC Physical Design Engineer at Synopsys

Elevate your career at Synopsys as an ASIC Physical Design Engineer, contributing to advanced test chip development. Leverage your expertise in physical design to optimize high-performance ASIC solutions.
Join a collaborative team focused on implementing and validating complex SoC and test chip architectures. Your deep understanding of physical design flow, including floor planning and tape-out, will be crucial. Utilize state-of-the-art tools and methodologies to ensure optimal area, power, and performance across various designs.

Key Responsibilities:

• Contribute to physical design for DDR/HBM/UCIe test chips

• Develop tailored floor plans and power strategies

• Own RTL-to-GDSII flow, ensuring design convergence

• Execute static timing analysis and physical verification

• Drive tool flow automation and debugging tasks
Requirements:

• 6 to 7 years in ASIC physical design experience

• Proficiency in CAD tools like Prime Time and IC Compiler II

• Deep understanding of ASIC physical design flow

• Familiarity with IP integration and verification flows

• Experience leading complex, cross-functional projects
Utilize your physical design expertise to drive innovation and enhance product reliability at Synopsys.
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