Senior Technical Staff Engineer - Analog Design

Job Description

Microchip's Timing and Communication Group (TCG) is seeking a Senior Technical Staff Engineer – Analog Design to provide technical leadership and architectural direction across the development of advanced analog and mixed-signal IP for next‑generation timing solutions.

This role is designed for a highly experienced industry analog designer with deep technical expertise, strong system‑level thinking, and a proven ability to guide design teams through complex mixed‑signal challenges. The position combines hands‑on technical contribution with technical leadership and mentoring responsibilities.

• Define architecture, specifications, and design methodologies for high‑performance analog IP, including PLLs, DLLs, ADCs, DACs, filters, high‑speed I/O interfaces, and related circuits used in TCG products
• Drive top‑level mixed‑signal system architecture to ensure robust integration of analog IP within complex SoC environments
• Influence long‑term analog IP direction and contribute to product roadmap discussions

• Provide senior‑level technical guidance to analog design teams through design reviews, modeling strategy, simulation methodology, and silicon bring‑up
• Serve as a technical resource and mentor for junior and mid‑level designers, supporting sound design decisions and skill development
• Influence design trade‑offs, verification approaches, and modeling strategies across multiple projects

• Lead transistor‑level design and advanced simulations across process corners and operating conditions
• Develop and review behavioral and Verilog‑A models to support efficient mixed‑signal SoC simulation
• Guide silicon validation, characterization, test planning, and system‑level laboratory evaluation

• Partner closely with architects, digital and mixed‑signal designers, layout teams, product engineers, and multi‑site engineering groups
• Support first‑pass silicon success through disciplined design execution and cross‑team coordination

• Master’s degree or Doctorate in Electrical Engineering or a closely related field
• 10+ years of industry experience in analog and mixed‑signal IC design
• Proven experience designing high‑speed and analog circuits such as PLLs/DLLs, ADCs/DACs, filters, and high‑speed I/O
• Strong fundamentals in device physics, circuit theory, and layout‑aware design
• Extensive experience with Cadence IC design tools and flows
• Hands‑on experience with scripting and automation (e.g., Skill, Python, Perl, Tcl)
• Strong communication skills and experience working effectively in multi‑site engineering teams

• Advanced academic study or research in analog or mixed‑signal design that strengthens system‑level insight or modeling approaches
• Experience applying research concepts to practical, production‑ready silicon
• Expertise in mixed‑signal system‑level design and architecture
• Strong proficiency in Verilog‑A for analog behavioral modeling
• Experience with silicon bring‑up, debug, and characterization in lab environments
• Exposure to MEMS analog interface circuits

Microchip provides a technically rigorous, stable environment where senior engineers can apply deep expertise, influence long‑term product direction, and mentor the next generation of designers. The company values disciplined engineering, collaboration, and delivering reliable products that customers depend on for the long term.

Travel: 0% – 25%

Pay Range: $153,000 – $203,000 (annual base salary, dependent on location, skills and experience). Total compensation includes base pay, restricted stock units, quarterly bonus, health benefits beginning day one, retirement savings plans, and an industry‑leading IESPP program with a 6‑month look‑back feature.

In accordance with applicable laws (including human rights and accessibility legislation in Ontario), accommodation will be provided in all parts of the hiring process. If you would like to contact us about the website or need help completing the application process, please email This contact information is for accommodation requests only and cannot be used to inquire about the status of applications.