Principal Analog Layout Engineer

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Principal Analog Layout Engineer page is loaded## Principal Analog Layout Engineer locations:
Ottawa time type:
Full time posted on:
Publié aujourd'huijob requisition :
R030799

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions and are one of the main contributors to Ciena's success in the telecommunications industry. Successful candidates will be joining a vibrant team with a proven track-record of success over 30-years of evolution and revolution in the advancement of high-speed circuits used in broadband fiber-optic modems. This team pioneered the introduction of the world’s first high-speed DAC and ADC analog macros that ushered in the era of coherent fiber-optic product solutions.

To further strengthen our team, we are looking for a hardworking analog layout engineer who will be working on advanced high-speed analog design circuits in the latest deep-submicron  CMOS and/or BiCMOS technologies.

Your role as an analog layout engineer will be to drive and implement best-in-class high-speed analog layouts that extract the highest performance from the world’s most advanced CMOS and BiCMOS technologies.  These analog macros include electrical interface-facing DAC and ADC based SERDES solutions for 112G and 224G, optical-line-facing high-speed DAC and ADC circuits interfacing with optical modulators and detectors, transimpedance amplifiers, modulator driver circuits, and critical precision analog circuits for control and monitoring functions, etc.
** Responsibilities:
*** Develop block and macro level layouts including floor-planning, placement, routing and optimization.
* Carry out layout feasibility studies on various circuit designs in collaboration with senior analog designers. The goal will be to find the best possible solution considering various trade-offs and discussions with team members.
* Write automation scripts for layout flow improvements including pcells.
* Conduct thorough verification checks such as DRC, ANT, LVS, PERC, EM, IR to ensure the final layout possesses the highest level of quality.
* Debug ESD violations reported by PERC and suggest solutions.
* Investigate new features within the layout tools and processes used for creating layouts with the aim of enhancing productivity.
* Mentor junior layout team members as applicable who may assist with some aspects of the overall layout implementation
* Provide regular status updates, participate in team meetings and share experiences with the rest of the group.
* Bachelor's or higher degree in Electrical Engineering or related field, with 5+ years of relevant industry experience.
* Experience in custom analog and mixed signal layout design with a strong knowledge of deep sub-micron CMOS devices (e.g. Finfet transistors).
* Highly motivated with strong team player…