FPGA Design Engineer – FPGA​/SystemVerilog​/CDC​/Synthesis​/Timing Closure​/Digital Design

FPGA Design Engineer – FPGA / System Verilog / CDC / Synthesis / Timing Closure / Digital Design

We are currently partnered with a growing technology and engineering organisation developing advanced hardware and communications solutions. As part of their continued expansion, they are looking to hire an experienced FPGA Design Engineer to take ownership of FPGA designs from initial specification and micro-architecture through implementation, synthesis, timing closure, and production.

• Design and implement FPGA logic using System Verilog
• Translate specifications into robust FPGA micro-architectures and production-quality implementations
• Take ownership of FPGA designs through the complete development lifecycle
• Develop timing-clean FPGA implementations and drive designs through timing closure
• Analyse and manage Clock Domain Crossings (CDC)
• Develop appropriate synchronization strategies and ensure reliable clock-domain interfaces
• Perform CDC analysis and contribute to CDC verification activities
• Own and maintain the FPGA synthesis flow

• 10–15 years of hands‑on FPGA design experience or equivalent depth of practical FPGA engineering experience
• Strong and current experience developing FPGA designs using System Verilog
• Proven ability to take ownership of complex FPGA designs and deliver them through implementation
• Strong practical knowledge of Clock Domain Crossing (CDC) analysis and implementation
• Experience developing and implementing FPGA synchronization strategies
• Hands‑on experience configuring and managing FPGA synthesis tools
• Experience with UVM‑based verification environments
• Experience developing automation and engineering scripts using Tcl, Python, or similar languages
• Familiarity with high-speed digital interfaces

Keywords

FPGA Design Engineer / FPGA Engineer / FPGA Design / FPGA Development / Digital Design / Digital Logic / System Verilog / RTL / RTL Design / FPGA Micro-Architecture / Clock Domain Crossing / CDC / CDC Analysis / CDC Verification / Synchronisation / FPGA Synthesis / Synthesis Tools / Timing Constraints / SDC / Static Timing Analysis / Timing Analysis / Timing Closure / Timing Optimisation / Congestion / Resource Utilisation / Hardware Design / Digital Electronics / UVM / FPGA Verification / Functional Verification / Tcl / Python / Design Automation / High-Speed Interfaces / High-Speed Digital Design / Optical Communications / Networking / Communications Products / Communications Systems / Production FPGA / Hardware Integration / Systems Engineering / Technical Design / Design Reviews / Technical Documentation / Design Ownership / Design Lead / Design Prime / FPGA Development Flow / FPGA Implementation / FPGA Timing / Hardware Engineering / Embedded Hardware

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