Mixed Signal Design Engineer

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

The Wavelogic family of products is widely used in Ciena's optical fiber transmission solutions and is one of the main contributors to Ciena's success in the telecommunications industry. Successful candidates will be joining a vibrant team with a proven track record of success over 30 years of evolution and revolution in the advancement of high-speed circuits used in broadband fiber-optic modems.

This team pioneered the introduction of the world’s first high-speed DAC and ADC analog macros that ushered in the era of coherent fiber-optic product solutions.

• Designing the high precision Sigma-Delta DAC and ADC for control and monitoring
• Designing the System Verilog models for various analog macros
• Designing the IBIS-AMS models for the high-speed DAC and ADC based Ser Des IP running at 56
  
  Gbd, 112
  
  Gbd, 224
  
  Gbd, and 448
  
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• Creating Design Specification Document
• Interacting with and providing support to the system team, analog team, the digital team, the DSP team, the signal integrity team, the hardware team, firmware team, and the analog lab bring-up team.

• Electrical or computer engineering, computer science or other applicable scientific degree at the BEng/BSc, MEng/MSc, or PhD level
• Design experience in the latest CMOS and BiCMOS technology
• Proficiency with Cadence Virtuoso/Xcelium/AMS, Synopsys VCS/StarRC, Siemens Questa/Formal/Calibre/SymphonyAMS/AFS
• Familiarity with System Verilog, VerilogAMS, VerilogA, Matlab/Simulink, C/C++, Python languages
• Ability to work independently and collaboratively with team members
• Skills of writing and presenting in English

• Knowledge of UVM, Git, Gradle, Google Tests
• Experience with the RF and Signal Integrity tools DSP, digital, and analog design and modelling in high Ser Des application
• AI tools for automation

The annual salary range for this position is $90,600 - $144,800 CAD.

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available. Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission.

In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

Dig deeper into who we are, what we do, and what you can expect as a member of our team. Meet the people who are shaping the future of communication and explore the culture we’ve built together at Ciena Life.