Stefanini Group in Ottawa is seeking an FPGA Design Engineer with 4G/5G radio experience for an onsite, long-term contract in Kanata, Ontario, Canada. The role requires heavy Verilog/System Verilog RTL, DSP skills, and expertise with /LTE protocols.
You will design FPGA IP, implement RTL, verify with UVM, and collaborate with radio and software teams. Ideal candidates have 7+ years in FPGA design, experience with 4G/5G radios, and proficiency with Quartus, Vivado, MATLAB/Simulink.
The following opportunity is for a Senior FPGA Engineer - 4G/5G Radio DSP & RTL with Stefanini.
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This posting is for the Senior FPGA Engineer - 4G/5G Radio DSP & RTL role at Stefanini, based in Ottawa, ON, Canada.
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