Sr Package Design Engineer

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

Having spent a decade or more working at the intersection of silicon, packaging, and board design, you know where good architectures succeed and where they fail. Evaluating package architectures, reviewing power delivery networks and bump maps, and turning SI/PI and EM analysis into sound engineering decisions are all part of your toolkit. When faced with ambiguity, you know how to focus on the issues that matter and keep complex programmes moving forward.

At Synopsys, you'll lead package design for advanced IP test chips at the forefront of performance. Working with tools such as Ansys HFSS and collaborating across engineering teams, you'll help shape the technologies that enable the next generation of semiconductor products. Just as importantly, you'll bring the confidence to challenge assumptions, ask the right questions, and drive decisions that move the design forward.

• Lead four to six test-chip package designs per year from requirements definition through final delivery, coordinating across internal teams, customers, and external partners
• Define package requirements early in the design cycle, including bump maps, ball maps, and layer stack-up decisions that optimize signal integrity and power integrity performance
• Perform hands-on physical design and layout of advanced package substrates using industry-standard EDA tools
• Extract electrical models from substrate designs using 3D EM simulation tools like Ansys HFSS, and analyze them against SI and PI requirements to validate performance
• Guide customers through package architecture evaluations and trade-off analysis to identify implementation options that work for Synopsys IP
• Resolve complex package design and integration issues by developing technically sound solutions that balance electrical performance, manufacturability, and cost
• Provide regular project updates to management covering progress, technical risks, dependencies, mitigation plans, and decisions that need escalation

• Enable successful tape-outs of Synopsys IP test-chips by ensuring package designs meet electrical and physical performance requirements from day one
• Reduce design iteration cycles and avoid costly respins by catching signal integrity and power integrity issues early through rigorous modeling and analysis
• Expand the range of package solutions available to Synopsys customers by evaluating new architectures and proving out their viability for high-performance IP
• Strengthen customer relationships by providing expert guidance on package design decisions that directly affect their product success
• Improve design quality and efficiency across the team by establishing best practices for substrate layout, model extraction, and SI/PI validation
• Accelerate time-to-market for Synopsys IP by coordinating design phases, technical reviews, and hand-offs that keep projects moving without…