ASIC​/FPGA Design Verification Engineer, Sr

Qualcomm Canada ULC

Engineering Group, Engineering Group > ASICS Engineering

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products.

Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Replacement Position

• Deliver standards-compliant IP blocks and subsystems for PCIe Gen7 (and beyond), CXL 4.0 (and beyond), UALink, Ethernet, and next-generation high-speed interconnect ASICs and FPGAs.
• Provide technical leadership for verification activities across IP, subsystem, and system-level designs.
• Architect, develop, and document scalable verification environments using System Verilog and UVM.
• Develop comprehensive verification test plans and drive verification closure.
• Develop, debug, and optimize complex test cases to achieve functional and coverage goals.
• Drive bug tracking, root-cause analysis, and issue resolution from discovery through closure.
• Improve engineering productivity through advanced tools, AI-driven verification techniques, automation, and scripting solutions.
• Collaborate closely with architecture, design, software, validation, and customer teams to ensure successful product execution.
• Mentor junior and senior engineers, promoting technical excellence and verification best practices across the organization.

• MSc/MEng with 7+ years of experience, or BSc/BEng with 10+ years of experience in ASIC or FPGA development and verification.
• Deep knowledge of high-speed communication and interconnect protocols such as PCIe, CXL, UALink, and Ethernet.
• Expert-level experience with System Verilog, UVM, constrained-random, and coverage-driven verification methodologies.
• Strong understanding of IP, subsystem, and SoC-level verification.
• Extensive experience with simulation, debugging, verification closure, functional coverage, and assertion-based verification.
• Excellent technical leadership, communication, and problem-solving skills.
• Ability to influence technical direction and drive alignment across cross-functional teams.

• Experience with PCIe Gen5/6/7 or CXL 3.0/4.0 from Physical Layer through Transaction Layer.
• Experience with UALink and next-generation AI/HPC interconnect technologies.
• Experience using PCIe/CXL VIPs from Siemens/Avery, Cadence, or Synopsys.
• Experience leveraging AI-based approaches to improve verification productivity, test generation, debug, and coverage closure.
• Experience with formal verification, emulation, or FPGA prototyping.
• Experience defining or deploying verification methodologies used across multiple projects or teams.

• Recognized as a technical leader who drives execution and delivers results.
• Strong mentoring and coaching skills with a passion for developing engineers.
• Detail-oriented with exceptional analytical and…