Advanced SerDes & Analog​/Mixed-Signal IC Design Intern – Summer

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $500M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical.

Our team is talent-dense andhigh-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard.

About the Role

Upscale AI is developing next-generation high-speed connectivity solutions for AI infrastructure and data centers. We are looking for highly motivated summer interns to work alongside our experienced engineering team on advanced Ser Des and analog/mixed-signal integrated circuit design.

This internship offers hands-on opportunities to explore challenging problems at the intersection of high-speed circuit design, digital signal processing, and AI-driven engineering methodologies. Depending on your background and interests, you may contribute to one or more of the following areas:

• High-Speed ADC Design and Modeling: Research and develop high-performance ADC architectures for next-generation Ser Des receivers, including sampling architectures, time-interleaved ADCs, calibration techniques, and optimization of speed, resolution, power, and linearity.
• Foundation IP Development: Contribute to the design, modeling, characterization, and optimization of foundation analog/mixed-signal IP blocks that enable next-generation Ser Des, including clocking, data conversion, calibration, and related circuit building blocks.
• AI-Driven Circuit Design: Develop and apply AI/ML techniques to accelerate circuit design, optimization, modeling, and verification. Explore automated design-space exploration, intelligent parameter optimization, surrogate modeling, and AI-assisted engineering workflows.
• Ultra-Low-Jitter PLL Design and Modeling: Explore advanced PLL architectures for high-speed communication systems, including low-jitter clock generation, digitally intensive PLL architecture and design. Investigate phase-noise performance, jitter optimization, and high-precision modeling of the PLL in the digital domain.

What You’ll Do

• Collaborate with experienced engineers to investigate challenging circuit and system-level design problems.
• Develop analytical models, behavioral simulations, and circuit-level simulations to evaluate new architectures and design approaches.
• Build scripts and tools to automate simulation, data analysis, optimization, and design workflows.
• Explore novel algorithms and circuit techniques to improve performance, power efficiency, robustness, and design productivity.
• Present technical findings, simulation results, and design recommendations to the engineering team.
• Where appropriate, contribute to circuit implementation, verification, characterization, or silicon measurement activities.

Qualifications:

• Currently pursuing an M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• Strong fundamentals in analog and mixed-signal circuit design, communication systems, signal processing, or related areas.
• Experience with circuit simulation, numerical analysis, or engineering computation.
• Proficiency in Python, MATLAB, or similar tools for modeling, automation, and data analysis.
• Strong analytical and problem-solving skills, with the ability to independently investigate…