Senior IC Layout Engineer

This is a new opportunity for a Senior IC Layout Engineer with an innovative deep-tech company specialising in advanced semiconductor technologies, based in Oxford. Hybrid working is available with this position, with a market-topping salary + RSU package.
As our client continues to scale their processor design team, they are looking for a Senior IC Layout Engineer to play a key role in taking complex chip designs from initial requirements through to physical implementation and tape-out.
This is a hands-on role suited to an experienced layout engineer who enjoys working closely with design, engineering, scientific and fabrication teams, and who is comfortable taking ownership of projects from concept through to final delivery.
Responsibilities
Take ownership of chip designs through the full development process, from requirements and specifications through to layout and tape-out
Translate system and design requirements into practical chip-level physical implementations
Design and lay out complex, multi-layer semiconductor devices, including detailed metal routing and interconnects
Consider interfaces and compatibility between different technologies and components within the overall design
Work closely with scientists, engineers and fabrication partners to understand requirements and resolve design constraints
Collaborate across multiple teams to ensure designs are technically feasible and compatible with manufacturing requirements
Identify and resolve layout and physical-design challenges throughout the development process
Take responsibility for individual projects and drive them through to successful tape-out
Contribute to improving layout methodologies, processes and automation within the wider design team
Requirements
We're looking for an experienced engineer with strong hands-on IC layout experience and an understanding of the wider chip design process. You should be comfortable working across disciplines, translating requirements into physical designs and understanding how different elements of a chip interact and constrain one another.
You will ideally have experience with:
Complex, multi-layer IC or semiconductor layout
Metal routing and physical implementation
Taking designs through to tape-out
Cadence or equivalent IC layout tools
Working with design rules, manufacturing constraints and physical design requirements
Working collaboratively with scientists, engineers and fabrication teams
Taking ownership of technically complex projects and delivering them independently
For more details or to apply, get in touch with Caroline Pye.