Analog Mixed-Signal Design and Modelling Engineer

IonQ, Inc. [NYSE: IONQ] is the world’s leading quantum platform and merchant supplier - delivering integrated quantum solutions across computing, networking, sensing, and security. IonQ’s newest generation of quantum computers, the IonQ Tempo, is the latest in a line of cutting‑edge systems that have been helping customers and partners including Amazon Web Services, and AstraZeneca achieve 20x performance results and accelerate innovation in drug discovery, materials science, financial modeling, logistics, cybersecurity, and defense.

In 2025, the company achieved 99.99% two‑qubit gate fidelity, setting a world record in quantum computing performance.

Headquartered in College Park, Maryland, IonQ has operations in California, Colorado, Massachusetts, Tennessee, Washington, Italy, South Korea, Sweden, Switzerland, Canada, and the United Kingdom. Our quantum computing services are available through all major cloud providers, while we also meet the needs of networking and sensing customers across land, sea, air, and space. IonQ is making quantum platforms more accessible and impactful than ever before.

This role is based at our Oxford, England (UK) office, with the option to work a few days a week remotely.

Up to 5%

1765

We are looking for a Staff Analog Mixed‑Signal Design and Modelling Engineer to join our Cryo‑CMOS IC team at IonQ Oxford. In this role, you will develop behavioural models and mixed‑signal verification environments for ASICs used in our trapped‑ion quantum processors.

Working with analog designers, architecture and system teams, you will verify block and full‑chip behaviour, correlate models with circuit simulations and measured silicon, and support tape‑out and silicon bring‑up. At Staff level, you will lead the AMS modelling and verification methodology, make technical decisions on model accuracy and simulation performance, and mentor other engineers. You'll play an important part in shaping the design, modelling and verification methodology, standards and sign‑off criteria that support our work in building the world's most advanced quantum systems.

In this position, you will build and maintain the model of the chip that the whole team simulates against, a mixed‑abstraction model combining transistor‑level circuits with Verilog‑A/Verilog‑AMS and System Verilog real‑number behavioural blocks. These models will be derived from first‑principles mathematics and correlated against schematic and measured silicon. You will decide which blocks are represented at which level of abstraction, keep the models faithful to the schematics and measured silicon.

The full‑chip model will then be used to verify the ASICs that control the quantum processor from room temperature down to a few kelvin.

You will develop verification plans, run simulations and regressions, and validate models against circuit simulations and available silicon measurements. As a Staff Engineer, you will lead modelling and verification reviews, help define sign‑off criteria and mentor other engineers. Your work will support tape‑out and silicon bring‑up, helping deliver reliable control electronics for IonQ’s quantum computing systems.

Key responsibilities include:

• Own the full‑chip modelling strategy: model architecture, abstraction levels, accuracy targets and sign‑off criteria used across the IC development flow
• Owning analog and mixed‑signal blocks (references, DACs, switches, regulators, clock distribution) from specification through schematic design
• Own top‑level integration: define block interfaces and specifications, assemble the top level, and run the full‑chip mixed‑signal simulations that verify the ASIC
• Develop Verilog‑A and Verilog‑AMS models of analog blocks…