Senior Silicon Validation Engineer

Senior Silicon Validation Engineer at IonQ, Oxford, England, United Kingdom. A senior-level full time position in the Compute - Engineering team, listed under hardware engineering.

We are looking for a Senior Silicon Validation Engineer to join our Cryo-CMOS IC team at IonQ Oxford. You will lead the validation and characterisation of analogue and mixed-signal ASICs for our trapped-ion quantum processors, from test planning and platform development through first-silicon bring-up, debug and system integration.

This is a hands-on technical role. You will shape our validation architecture, build reusable hardware and software, and provide the evidence needed to make confident silicon acceptance decisions. The work includes room-temperature silicon validation and silicon characterisation at cryogenic temperatures (around 4 kelvin), on packaged parts, chip-on-board assemblies and bare die on a cryogenic probe station.

You will own validation delivery across chip and system interfaces, working closely with analogue and digital design, verification, modelling, firmware and systems engineers. You will turn requirements into measurable tests, prepare platforms before silicon arrives and resolve failures across the chip, board and software.

As a Senior engineer, you will set technical standards, guide other engineers and improve coverage, repeatability and test efficiency across successive ASIC generations.

You will bring substantial experience in analogue or mixed-signal silicon validation and characterisation, with ownership of multiple silicon bring-up programmes. A degree in electrical or electronic engineering, or equivalent practical experience, is expected. You should combine hands‑on laboratory skills with sound judgement on test coverage, measurement confidence and programme risk.

Strong electronics fundamentals and experience validating precision signal chains, data converters or power‑management circuits, including their digital control interfaces.

• Own the silicon validation strategy, plans, acceptance criteria and readiness reviews, with traceability from block and system requirements to tests, results and unresolved risks.
• Present the silicon acceptance report to the Cryo-CMOS IC Lead and programme stakeholders.
• Lead first‑silicon bring‑up and characterisation of sample‑and‑hold and switch arrays, DACs, ADCs, references, amplifiers, switches, regulators, clocking and device‑level test structures, across supply, temperature, operating modes and device variation, with sound calibration and measurement uncertainty.
• Develop validation boards, fixtures and reusable Python automation, instrument drivers and regression suites, addressing signal integrity, grounding, power integrity and measurement access, with version‑controlled tests and reproducible data analysis.
• Plan and lead cryogenic measurements with specialist colleagues, including bare‑die probing and the cold signal chain, and drive failures to root cause, separating silicon defects from board, firmware and test artefacts and correlating results with simulations, device models and foundry or partner data.
• Influence testability before tape‑out, coordinate validation with external design partners, the foundry and other IonQ sites.
• Lead technical reviews, mentor engineers and document methods to improve throughput, data quality and reuse.